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32 VLSI Test Principles and Architectures 1.5.8 Boundary Scan Testing In the mid-1980s, the Joint Test Action Group (JTAG) proposed a boundary scan standard, approved in 1990 as IEEE Standard 1149.1 [IEEE 1149.1-2001]. Bound- ary scan, based on the basic idea of scan design, inserted logic to provide a scan path through all I/O buffers of ICs to assist in testing the assembled PCB. A typical boundary scan cell is illustrated in Figure 1.15 with regard to its application to a bidirectional I/O buffer. The scan chain provides the ability to shift in test vectors to be applied through the pad to the pins and interconnections on the PCB. The output responses are captured at the input buffers on other devices on the PCB and subsequently shifted out for fault detection. Thus, boundary scan provides access to the various signal nodes on a PCB without the need for physical probes. The test access port (TAP) provides access to the boundary scan chain through
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Unformatted text preview: a four-wire serial bus interface (summarized in Table 1.5) in conjunction with instructions transmitted over the interface. In addition to testing the interconnec-tions on the PCB, the boundary scan interface also provides access to DFT features, such as LSSD or BIST, designed and implemented in the VLSI devices for board and system-level testing. The boundary scan description language (BSDL) pro-vides a mechanism with which IC manufacturers can describe testability features in Input data to IC capture FF Capture update FF Update Input Scan In Shift Scan Out Output Input BS Cell Control BS Cell Pad Output BS Cell 1 1 ± FIGURE 1.15 Basic boundary scan cell applied to a bidirectional buffer. TABLE 1.5 ± Boundary Scan Four-Wire Interface BS pin I/O Function TCK Input Test clock TMS Input Test mode select TDI Input Test data in TDO Output Test data out...
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This note was uploaded on 05/16/2011 for the course ENGINEERIN mp108 taught by Professor Elbarki during the Spring '08 term at Alexandria University.

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