64_pdfsam_VLSI TEST PRINCIPLES & ARCHITECTURES

64_pdfsam_VLSI TEST PRINCIPLES & ARCHITECTURES -...

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Introduction 33 a chip [Parker 2001]. In 1999, another boundary scan standard, IEEE 1149.4, was adopted for mixed-signal systems; it defines boundary scan cells as well as a TAP for the analog portion of the device [IEEE 1149.4-1999] [Mourad 2000]. In 2003, an extended boundary scan standard for the I/O protocol of high-speed networks, namely 1149.6, was approved [IEEE 1149.6-2003]. System-on-chip implementations face test challenges in addition to those of nor- mal VLSI devices. SOCs incorporate embedded cores that may be difficult to access during testing. The IEEE P1500 working group was approved in 1997 to develop a scalable wrapper architecture and access mechanism similar to boundary scan for enabling test access to embedded cores and the associated interconnect between embedded cores. This proposed P1500 test method, approved as an IEEE 1500 standard in 2005 [IEEE 1500-2005], is independent of the underlying functionality of the SOC or its individual embedded cores and creates the necessary testability
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