65_pdfsam_VLSI TEST PRINCIPLES & ARCHITECTURES

65_pdfsam_VLSI TEST PRINCIPLES & ARCHITECTURES -...

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34 VLSI Test Principles and Architectures x 1 x 2 x 3 x n parity ± FIGURE 1.17 Circuit for Problem 1.4. 1.2 (Bridging Fault Models) Show an example where a combinational logic circuit will become a sequential circuit in the presence of a bridging fault. 1.3 (Automatic Test-Pattern Generation) Generate a minimum set of test vec- tors to completely test an n -input NAND gate under the single stuck-at fault model. How many test vectors are needed? 1.4 (Automatic Test-Pattern Generation) Generate a minimum set of test vec- tors to detect all single stuck-at faults for a cascade of ( n 1) exclusive- OR gates for an n -bit parity checker, as shown in Figure 1.17, where each exclusive-OR gate is implemented by elementary logic gates (AND, OR, NAND, NOR, NOT). How many test vectors are needed? 1.5 (Mean Time between Failures) The number of failures in 10 9 hours is a unit (abbreviated FITS) that is often used in reliability calculations. Calculate the MTBF for a system with 500 components where each component has a failure rate of 1000 FITS. 1.6
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Unformatted text preview: (Mean Time to Repair) On average, how long would it take to repair a system each year if the availability of the system is 99.999%? 1.7 (Defect Level) What percentage of all parts shipped will be defective if the yield is 50% and the fault coverage is 90% for the set of test vectors used to test the parts? Acknowledgments The authors wish to acknowledge the following people for their assistance during the preparation of this chapter: Dr. Huawei Li of the Institute of Computing Tech-nology at the Chinese Academy of Sciences, Sachin Dhingra and Sudheer Vemula of the Department of Electrical and Computer Engineering at Auburn University, and Prof. Wen-Ben Jone of the Department of Electrical & Computer Engineering and Computer Science at the University of Cincinnati. References R1.0—Books [Abramovici 1994] M. Abramovici, M. A. Breuer, and A. D. Friedman, Digital Systems Testing and Testable Design , IEEE Press, Piscataway, NJ, 1994 (revised printing)....
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