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36 VLSI Test Principles and Architectures [Brglez 1985] F. Brglez and H. Fujiwara, A neutral netlist of 10 combinational benchmark designs and a special translator in Fortran, in Proc. Int. Symp. on Circuits and Systems , June 1985, pp. 663–698. [Brglez 1989] F. Brglez, D. Bryan, and K. Kozminski, Combinational profiles of sequen- tial benchmark circuits, in Proc. Int. Symp. on Circuits and Systems , May 1989, pp. 1929–1934. [Eichelberger 1977] E. B. Eichelberger and T. W. Williams, A logic design structure for LSI testability, in Proc. Des. Automat. Conf. , June 1977, pp. 462–468. [Fujiwara 1983] H. Fujiwara and T. Shimono, On the acceleration of test generation algo- rithms, IEEE Trans. Comput. , C-32(12), 1137–1144, 1983. [Gelsinger 2000] P. Gelsinger, Discontinuities driven by a billion connected machines, IEEE Design Test Comput. , 17(1), 7–15, 2000. [Goel 1981] P. Goel, An implicit enumeration algorithm to generate tests for combinational logic circuits, IEEE Trans. Comput. , C-30(3), 215–222, 1981. [Goldstein 1979] L. H. Goldstein, Controllability/observability analysis of digital circuits, IEEE Trans. Circuits Syst. , CAS-26(9), 685–693, 1979. [IEEE 1149.4-1999] IEEE Std. 1149.4-1999,
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