68_pdfsam_VLSI TEST PRINCIPLES & ARCHITECTURES

68_pdfsam_VLSI TEST PRINCIPLES & ARCHITECTURES -...

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CHAPTER 2 D ESIGN FOR T ESTABILITY Laung-Terng (L.-T.) Wang SynTest Technologies, Inc., Sunnyvale, California Xiaoqing Wen Kyushu Institute of Technology, Fukuoka, Japan Khader S. Abdel-Hafez SynTest Technologies, Inc., Sunnyvale, California ABOUT THIS CHAPTER This chapter discusses design for testability (DFT) techniques for testing modern digital circuits. These DFT techniques are required in order to improve the quality and reduce the test cost of the digital circuit, while at the same time simplifying the test, debug and diagnose tasks. The purpose of this chapter is to provide readers with the knowledge to judge whether a design is implemented in a test-friendly manner and to recommend changes in order to improve the testability of the design for achieving the above-mentioned goals. More specifically, this chapter will allow readers to be able to identify and fix scan design rule violations and understand the basics for successfully converting a design into a scan design.
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