CHAPTER 2DESIGN FORTESTABILITYLaung-Terng (L.-T.) WangSynTest Technologies, Inc., Sunnyvale, CaliforniaXiaoqing WenKyushu Institute of Technology, Fukuoka, JapanKhader S. Abdel-HafezSynTest Technologies, Inc., Sunnyvale, CaliforniaABOUT THIS CHAPTERThis chapter discussesdesign for testability(DFT) techniques for testing moderndigital circuits. These DFT techniques are required in order to improve the qualityand reduce the test cost of the digital circuit, while at the same time simplifying thetest, debug and diagnose tasks. The purpose of this chapter is to provide readerswith the knowledge to judge whether a design is implemented in a test-friendlymanner and to recommend changes in order to improve the testability of the designfor achieving the above-mentioned goals. More specifically, this chapter will allowreaders to be able to identify and fix scan design rule violations and understand thebasics for successfully converting a design into a scan design.
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This note was uploaded on 05/16/2011 for the course ENGINEERIN mp108 taught by Professor Elbarki during the Spring '08 term at Alexandria University.