Design for Testability 39 and check from external pins. Difficulties in controlling and observing the internal states of sequential circuits led to the adoption of structured DFT approaches in which direct external access is provided for storage elements. These reconfigured storage elements with direct external access are commonly referred to as scan cells . Once the capability of controlling and observing the internal states of a design is added, the problem of testing the sequential circuit is transformed into a problem of testing the combinational logic, for which many solutions already existed. Scan design is currently the most popular structured DFT approach. It is imple-mented by connecting selected storage elements of a design into multiple shift registers, called scan chains , to provide them with external access. Scan design accomplishes this task by replacing all selected storage elements with scan cells, each having one additional scan input (SI) port and one shared/additional
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