Info iconThis preview shows page 1. Sign up to view the full content.

View Full Document Right Arrow Icon
40 VLSI Test Principles and Architectures at the RTL, thereby reducing test development time and creating reusable and testable RTL cores. This further allows the integrated DFT design to go through synthesis-based optimization to reduce performance and area overhead. 2.2 TESTABILITY ANALYSIS Testability is a relative measure of the effort or cost of testing a logic circuit. In general, it is based on the assumption that only primary inputs and primary outputs can be directly controlled and observed, respectively. Testability reflects the effort required to perform the main test operations of controlling internal signals from primary inputs and observing internal signals at primary outputs. Testability analysis refers to the process of assessing the testability of a logic circuit by calculating a set of numerical measures for each signal in the circuit. One important application of testability analysis is to assist in the decision- making process during test generation. For example, if during test generation it
Background image of page 1
This is the end of the preview. Sign up to access the rest of the document.

This note was uploaded on 05/16/2011 for the course ENGINEERIN mp108 taught by Professor Elbarki during the Spring '08 term at Alexandria University.

Ask a homework question - tutors are online