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73_pdfsam_VLSI TEST PRINCIPLES &amp; ARCHITECTURES

# 73_pdfsam_VLSI TEST PRINCIPLES &amp; ARCHITECTURES - 42...

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42 VLSI Test Principles and Architectures TABLE 2.1 SCOAP Combinational Controllability Calculation Rules 0-Controllability (Primary Input, Output, Branch) 1-Controllability (Primary Input, Output, Branch) Primary Input 1 1 AND min {input 0-controllabilities} + 1 (input 1-controllabilities} + 1 OR (input 0-controllabilities) + 1 min {input 1-controllabilities} + 1 NOT Input 1-controllability + 1 Input 0-controllability + 1 NAND (input 1-controllabilities) + 1 min {input 0-controllabilities} + 1 NOR min {input 1-controllabilities} + 1 (input 0-controllabilities) + 1 BUFFER Input 0-controllability + 1 Input 1-controllability + 1 XOR min {CC1( a ) + CC1( b ), CC0( a ) + CC0( b )} + 1 min CC1 a + CC0 b CC0 a + CC1 b + 1 XNOR min {CC1( a ) + CC0( b ), CC0( a ) + CC1( b )} + 1 min CC1 a + CC1 b CC0 a + CC0 b + 1 Branch Stem 0-controllability Stem 1-controllability Note : a and b are inputs of an XOR or XNOR gate. TABLE 2.2 SCOAP Combinational Observability Calculation Rules Observability (Primary Output, Input, Stem) Primary Output 0 AND/NAND (output observability, 1-controllabilities of other inputs) + 1 OR/NOR (output observability, 0-controllabilities of other inputs) + 1
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