74_pdfsam_VLSI TEST PRINCIPLES &amp; ARCHITECTURES

74_pdfsam_VLSI TEST PRINCIPLES &amp; ARCHITECTURES - r...

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Design for Testability 43 2/3/3 2 /5/3 5/4/0 5/5/0 A B C in C out 3/3/2 1/1/4 1/1/5 3/3/5 1/1/7 Sum 1/1/5 1/1/4 1/1/4 1/1/4 1/1/4 3/3/2 1/1/4 ± FIGURE 2.1 SCOAP full-adder example. 2.2.1.2 Sequential Controllability and Observability Calculation Sequential controllability and observability measures are calculated in a similar manner as combinational measures, except thata1isnot added as we move from one level of logic gate to another; rather ,a1is added when a signal passes through a storage element. The difference is illustrated using the sequential circuit example shown in Figure 2.2, which consists of an AND gate and a positive-edge-triggered D
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Unformatted text preview: r . SCOAP measures of a D flip-flop with a synchronous, as opposed to asynchronous, reset are shown in [Bushnell 2000]. First, we calculate the combinational and sequential controllability measures of all signals. In order to control signal d to 0, either input a or b must be set to 0. In order to control d to 1, both inputs a and b must be set to 1. Hence, the combinational and sequential controllability measures of signal d are: CC0 ±d² = min ³ CC0 ±a²´ CC0 ±b²µ + 1 SC0 ±d² = min ³ SC0 ±a²´ SC0 ±b²µ CC1 ±d² = CC1 ±a² + CC1 ±b² + 1 SC1 ±d² = SC1 ±a² + SC1 ±b² Reset CK d Q q r a b D ± FIGURE 2.2 SCOAP sequential circuit example....
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