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75_pdfsam_VLSI TEST PRINCIPLES & ARCHITECTURES

75_pdfsam_VLSI TEST PRINCIPLES & ARCHITECTURES - 44...

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44 VLSI Test Principles and Architectures In order to control the data output q of the D flip-flop to 0, the data input d and the reset signal r can be set to 0 while applying a rising clock edge (a 0-to-1 transition) to the clock CK . Alternatively, this can be accomplished by setting r to 1 while holding CK at 0. Because a clock pulse is not applied to CK , a 1 is not added to the sequential controllability calculation in the second case; therefore, the combinational and sequential 0-controllability measures of q are: CC0 q = min CC0 d + CC0 CK + CC1 CK + CC0 r CC1 r + CC0 CK SC0 q = min SC0 d + SC0 CK + SC1 CK + SC0 r + 1 SC1 r + SC0 CK Here, CC0( q ) measures how many signals in the circuit must be set to control q to 0, whereas SC0( q ) measures how many flip-flops in the circuit must be clocked to set q to 0. The only way to control the data output q of the D flip-flop to 1 is to set the data input d to 1 and the reset signal r to 0 while applying a rising clock edge to the clock CK . Hence, CC1 q = CC1 d + CC0 CK + CC1 CK + CC0 r SC1 q = SC1 d + SC0 CK + SC1 CK + SC0 r + 1 Next, we calculate the combinational and sequential observability measures of
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