44VLSI Test Principles and ArchitecturesIn order to control the data outputqof the D flip-flop to 0, the data inputdand the reset signalrcan be set to 0 while applying a rising clock edge (a 0-to-1transition) to the clockCK. Alternatively, this can be accomplished by settingrto1 while holdingCKat 0. Because a clock pulse is not applied toCK, a 1 is notadded to the sequential controllability calculation in the second case; therefore, thecombinational and sequential 0-controllability measures ofqare:CC0q=minCC0d+CC0CK+CC1CK+CC0rCC1r+CC0CKSC0q=minSC0d+SC0CK+SC1CK+SC0r+1 SC1r+SC0CKHere, CC0(q) measures how many signals in the circuit must be set to controlqto0, whereas SC0(q) measures how many flip-flops in the circuit must be clocked tosetqto 0. The only way to control the data outputqof the D flip-flop to 1 is to setthe data inputdto 1 and the reset signalrto 0 while applying a rising clock edgeto the clockCK. Hence,CC1q=CC1d+CC0CK+CC1CK+CC0rSC1q=SC1d+SC0CK+SC1CK+SC0r+1Next, we calculate the combinational and sequential observability measures of
This is the end of the preview.
access the rest of the document.