48 VLSI Test Principles and Architectures transitions, and 1-to-0 transitions, which are then used to statistically profile the testability of a logic circuit. These data are then analyzed to find locations of poor testability. If a signal line exhibits only a few transitions or no transitions for the sample input patterns, it might be an indication that the signal likely has poor controllability. In addition to logic simulation, fault simulation has also been used to enhance the testability of a logic circuit using random or pseudo-random test patterns. For example, a random resistant fault analysis (RRFA) method has been suc-cessfully applied to a high-performance microprocessor to improve the circuit’s random testability in logic BIST [Rizzolo 2001]. This method is based on statis-tical data collected during fault simulation for a small number of random test patterns. Controllability and observability measures of each signal in the circuit are calculated using the probability models developed in the
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