80_pdfsam_VLSI TEST PRINCIPLES & ARCHITECTURES

80_pdfsam_VLSI TEST PRINCIPLES & ARCHITECTURES -...

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Unformatted text preview: Design for Testability 49 functional block in order to represent the flow of information and data dependen- cies. Each internal node of a DAG corresponds to a high-level operation (such as an arithmetic, relational, data transfer, and logical operation) of multiple bits, and each edge represents a signal, which can be composed of multiple bits. This mod- eling method keeps useful high-level information about a functional block while ignoring the details of the gate-level implementation. This information is then used to compute the 0-controllability, 1-controllability, and observability of each bit in a signal line. As an example, consider the n-bit ripple-carry adder shown in Figure 2.4, which consists of n 1-bit full-adders. By considering the minterms leading to a 1 on the respective output, the probability-based 1-controllability measures of s i and c i + 1 , denoted by C1( s i ) and C1( c i + 1 ), respectively, are calculated as follows [Boubezari 1999]: C1 s i = + C1 c i − 2 × ×...
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