Unformatted text preview: OP 1 , OP 2 , and OP 3 are designed to form a shift register so the required values can be shifted into the flip-flops using CP_input and used to control the destination ends of low-controllability nodes. As a result, the controllability of the circuit nodes is dramatically improved. This, however, results in additional delay to the logic path. Hence, care must be taken not to insert control points on a critical path. Furthermore, it is preferable...
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- Spring '08
- Logic gate, Flip-flops, Flip-flop, CK SI DI, Low-observability node, CP1 DI DI