83_pdfsam_VLSI TEST PRINCIPLES & ARCHITECTURES

83_pdfsam_VLSI TEST PRINCIPLES & ARCHITECTURES - OP...

Info iconThis preview shows page 1. Sign up to view the full content.

View Full Document Right Arrow Icon
52 VLSI Test Principles and Architectures SE 0 1 DQ DI SO CK OP 2 OP 3 Observation shift register OP_output DI SI SE SO SI SE DI SO SI SE Low-observability node A Logic circuit 1 Low-observability node B Low-observability node C OP 1 ± FIGURE 2.5 Observation point insertion. 0 1 Original connection DQ Control shift register DI SI SO DO TM DI SO SI TM Low-controllability node B DO TM CP_input CK DI SO SI TM DO Low-controllability node A Logic circuit Source Destination CP 1 Low-controllability node C CP 2 CP 3 ± FIGURE 2.6 Control point insertion. During test, TM is set to 1 so that the value from the D flip-flop drives the destina- tion end through the 1 port of the MUX. The D flip-flops in
Background image of page 1
This is the end of the preview. Sign up to access the rest of the document.

Unformatted text preview: OP 1 , OP 2 , and OP 3 are designed to form a shift register so the required values can be shifted into the flip-flops using CP_input and used to control the destination ends of low-controllability nodes. As a result, the controllability of the circuit nodes is dramatically improved. This, however, results in additional delay to the logic path. Hence, care must be taken not to insert control points on a critical path. Furthermore, it is preferable...
View Full Document

This note was uploaded on 05/16/2011 for the course ENGINEERIN mp108 taught by Professor Elbarki during the Spring '08 term at Alexandria University.

Ask a homework question - tutors are online