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54 VLSI Test Principles and Architectures Combinational logic X 1 Y 1 Q FF 3 QD Q D CK f 0 0 1 X 2 X 3 Y 2 D FF 2 FF 1 ± FIGURE 2.7 DifFculty in testing a sequential circuit. Shift register composed of n scan cells Test stimulus application Test response upload Test stimulus Test response 1 1 n n ± FIGURE 2.8 Scan design concept. without having to resort to applying an exponential number of clock cycles to force all storage elements to a desired internal state. Hence, the task of detecting fault f in Figure 2.7 becomes a simple matter of: (1) switching to shift mode and shifting in the desired test stimulus, 1 and 0, to FF 2 and FF 3 , respectively; (2) driving a 0
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Unformatted text preview: onto primary input X 3 ; (3) switching to capture mode and applying one clock pulse to capture the fault effect into FF 1 ; and, finally, (4) switching back to shift mode and shifting out the test response stored in FF 1 , FF 2 , and FF 3 for comparison with the expected response. Because scan design provides access to internal storage elements, test generation complexity is reduced. In the following two sections, a number of popular scan cell designs and scan architectures for supporting scan design are described in more detail....
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This note was uploaded on 05/16/2011 for the course ENGINEERIN mp108 taught by Professor Elbarki during the Spring '08 term at Alexandria University.

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