This preview shows page 1. Sign up to view the full content.
Unformatted text preview: onto primary input X 3 ; (3) switching to capture mode and applying one clock pulse to capture the fault effect into FF 1 ; and, finally, (4) switching back to shift mode and shifting out the test response stored in FF 1 , FF 2 , and FF 3 for comparison with the expected response. Because scan design provides access to internal storage elements, test generation complexity is reduced. In the following two sections, a number of popular scan cell designs and scan architectures for supporting scan design are described in more detail....
View Full Document
- Spring '08