Unformatted text preview: latch-based designs [Eichelberger 1977] [Eichelberger 1978] [DasGupta 1982]. Figure 2.12a shows a polarity-hold shift register latch (SRL) design described in [Eichelberger 1977] that can be used as an LSSD scan cell. This scan cell contains two latches, a master two-port D latch L 1 and a slave D latch L 2 . Clocks C , A , and B are used to select between the data input D and the scan input I to drive + L 1 and + L 2 . In an LSSD design, either + L 1 or + L 2 can be used to drive the combinational logic of the design. In order to guarantee race-free operation, clocks A , B , and C are applied in a nonoverlapping manner. In designs where + L 1 is used to drive the combinational...
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- Spring '08
- Electronic design automation, lssd scan cell