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88_pdfsam_VLSI TEST PRINCIPLES & ARCHITECTURES

88_pdfsam_VLSI TEST PRINCIPLES & ARCHITECTURES -...

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Design for Testability 57 (a) Q/SO SCK DI SI DCK D 1 D 2 D 3 D 4 D 1 (b) SCK DI SI DCK Q/SO T 2 T 1 T 3 T 4 T 3 ± FIGURE 2.11 Clocked-scan cell design and operation: (a) clocked-scan cell, and (b) sample waveforms. the current content of the clocked-scan cell is being shifted out. Sample operation waveforms are shown in Figure 2.11b. As in the case of muxed-D scan cell design, a clocked-scan cell can also be made to support scan replacement of a D latch. The major advantage of using a clocked- scan cell is that it results in no performance degradation on the data input. The major disadvantage, however, is that it requires additional shift clock routing. 2.4.3 LSSD Scan Cell While muxed-D scan cells and clocked-scan cells are generally used for edge- triggered, flip-flop-based designs, an LSSD scan cell is used for level-sensitive,
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Unformatted text preview: latch-based designs [Eichelberger 1977] [Eichelberger 1978] [DasGupta 1982]. Figure 2.12a shows a polarity-hold shift register latch (SRL) design described in [Eichelberger 1977] that can be used as an LSSD scan cell. This scan cell contains two latches, a master two-port D latch L 1 and a slave D latch L 2 . Clocks C , A , and B are used to select between the data input D and the scan input I to drive + L 1 and + L 2 . In an LSSD design, either + L 1 or + L 2 can be used to drive the combinational logic of the design. In order to guarantee race-free operation, clocks A , B , and C are applied in a nonoverlapping manner. In designs where + L 1 is used to drive the combinational...
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