89_pdfsam_VLSI TEST PRINCIPLES & ARCHITECTURES

89_pdfsam_VLSI TEST PRINCIPLES & ARCHITECTURES - A...

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58 VLSI Test Principles and Architectures + L 2 C D A I + L 1 L 1 L 2 SRL B (a) C D I + L 1 A B + L 2 D 1 D 2 D 3 D 4 T 1 T 2 T 3 T 4 D 1 (b) T 3 T 3 ± FIGURE 2.12 Polarity-hold SRL design and operation: (a) polarity-hold SRL, and (b) sample waveforms. logic, the master latch L 1 uses the system clock C to latch system data from the data input D and to output this data onto + L 1 . In designs where + L 2 is used to drive the combinational logic, clock B is used after clock A to latch the system data from latch L 1 and to output this data onto + L 2 . In both cases, capture mode uses both clocks C and B to output system data onto + L 2 . Finally, in shift mode, clocks
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Unformatted text preview: A and B are used to latch scan data from the scan input I and to output this data onto + L 1 and then latch the scan data from latch L 1 and to output this data onto + L 2 , which is then used to drive the scan input of the next scan cell. Sample operation waveforms are shown in Figure 2.12b. The major advantage of using an LSSD scan cell is that it allows us to insert scan into a latch-based design. In addition, designs using LSSD are guaranteed to...
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