Info iconThis preview shows page 1. Sign up to view the full content.

View Full Document Right Arrow Icon
Design for Testability 59 be race-free, which is not the case for muxed-D scan and clocked-scan designs. The major disadvantage, however, is that the technique requires routing for the additional clocks, which increases routing complexity. 2.5 SCAN ARCHITECTURES In this section, we describe three popular scan architectures. These scan architec- tures include: (1) full-scan design , where all storage elements are converted into scan cells and combinational ATPG is used for test generation; (2) partial-scan design , where a subset of storage elements is converted into scan cells and sequential ATPG is typically used for test generation; and (3) random-access scan design , where a random addressing mechanism, instead of serial scan chains, is used to provide direct access to read or write any scan cell. 2.5.1 Full-Scan Design In full-scan design, all storage elements are replaced with scan cells, which are then configured as one or more shift registers (also called scan chains ) during the
Background image of page 1
This is the end of the preview. Sign up to access the rest of the document.

This note was uploaded on 05/16/2011 for the course ENGINEERIN mp108 taught by Professor Elbarki during the Spring '08 term at Alexandria University.

Ask a homework question - tutors are online