90_pdfsam_VLSI TEST PRINCIPLES & ARCHITECTURES

90_pdfsam_VLSI TEST PRINCIPLES & ARCHITECTURES -...

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Design for Testability 59 be race-free, which is not the case for muxed-D scan and clocked-scan designs. The major disadvantage, however, is that the technique requires routing for the additional clocks, which increases routing complexity. 2.5 SCAN ARCHITECTURES In this section, we describe three popular scan architectures. These scan architec- tures include: (1) full-scan design , where all storage elements are converted into scan cells and combinational ATPG is used for test generation; (2) partial-scan design , where a subset of storage elements is converted into scan cells and sequential ATPG is typically used for test generation; and (3) random-access scan design , where a random addressing mechanism, instead of serial scan chains, is used to provide direct access to read or write any scan cell. 2.5.1 Full-Scan Design In full-scan design, all storage elements are replaced with scan cells, which are then configured as one or more shift registers (also called scan chains ) during the
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