92_pdfsam_VLSI TEST PRINCIPLES & ARCHITECTURES

92_pdfsam_VLSI TEST PRINCIPLES & ARCHITECTURES -...

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Design for Testability 61 scan cells are used to capture the test response from the combinational logic when a clock is applied. In general, combinational logic in a full-scan circuit has two types of inputs: primary inputs (PIs) and pseudo primary inputs (PPIs). Primary inputs refer to the external inputs to the circuit, while pseudo primary inputs refer to the scan cell outputs. Both PIs and PPIs can be set to any required logic values. The only difference is that PIs are set directly in parallel from the external inputs, and PPIs are set serially through scan chain inputs. Similarly, the combinational logic in a full-scan circuit has two types of outputs: primary outputs (POs) and pseudo pri- mary outputs (PPOs). Primary outputs refer to the external outputs of the circuit, while pseudo primary outputs refer to the scan cell inputs. Both POs and PPOs can be observed. The only difference is that POs are observed directly in parallel
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