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Unformatted text preview: case, the slave latch L 2 is used only for scan testing. Because LSSD designs use latches instead of flip-flops, at least two system clocks C 1 and C 2 are required to prevent combinational feedback loops from occurring. In this case, combinational logic driven by the master latches of the first system clock C 1 are used to drive the master latches of the second system clock C 2 , and vice versa. In order for this to work, the system clocks C 1 and C 2 should be applied in a nonoverlapping fashion. Figure 2.16a shows an LSSD single-latch design. Figure 2.16b shows an example of LSSD double-latch design [DasGupta 1982]. In normal mode, the C 1 and C 2 clocks are used in a nonoverlapping manner, where the C 2 clock is the same as the B clock. The testing of an LSSD full-scan X 2 Combinational logic X 3 X 1 Y 2 Y 1 PI PPI PO PPO SFF 1 SFF 2 SFF 3 SI SO DI Q SI DCK SCK DI Q SI DCK SCK DI Q SI DCK DCK SCK SCK ± FIGURE 2.15 Clocked full-scan circuit....
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This note was uploaded on 05/16/2011 for the course ENGINEERIN mp108 taught by Professor Elbarki during the Spring '08 term at Alexandria University.
- Spring '08