93_pdfsam_VLSI TEST PRINCIPLES & ARCHITECTURES

93_pdfsam_VLSI TEST PRINCIPLES & ARCHITECTURES - case,...

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62 VLSI Test Principles and Architectures 2.5.1.2 Clocked Full-Scan Design Figure 2.15 shows a clocked full-scan circuit implementation of the circuit given in Figure 2.13. Clocked-scan cells are shown in Figure 2.11a. This clocked full-scan circuit is tested using shift and capture operations, similar to a muxed-D full-scan circuit. The main difference is how these two operations are distinguished. In a muxed-D full-scan circuit, a scan enable signal SE is used, as shown in Figure 2.14a. In the clocked full-scan circuit shown in Figure 2.15, these two operations are distinguished by properly applying the two independent clocks SCK and DCK during shift mode and capture mode, respectively. 2.5.1.3 LSSD Full-Scan Design It is possible to implement LSSD full-scan designs, based on the polarity-hold SRL design shown in Figure 2.12a, using either a single-latch design or a double- latch design . In single-latch design [Eichelberger 1977], the output port + L 1 of the master latch L 1 is used to drive the combinational logic of the design. In this
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Unformatted text preview: case, the slave latch L 2 is used only for scan testing. Because LSSD designs use latches instead of flip-flops, at least two system clocks C 1 and C 2 are required to prevent combinational feedback loops from occurring. In this case, combinational logic driven by the master latches of the first system clock C 1 are used to drive the master latches of the second system clock C 2 , and vice versa. In order for this to work, the system clocks C 1 and C 2 should be applied in a nonoverlapping fashion. Figure 2.16a shows an LSSD single-latch design. Figure 2.16b shows an example of LSSD double-latch design [DasGupta 1982]. In normal mode, the C 1 and C 2 clocks are used in a nonoverlapping manner, where the C 2 clock is the same as the B clock. The testing of an LSSD full-scan X 2 Combinational logic X 3 X 1 Y 2 Y 1 PI PPI PO PPO SFF 1 SFF 2 SFF 3 SI SO DI Q SI DCK SCK DI Q SI DCK SCK DI Q SI DCK DCK SCK SCK ± FIGURE 2.15 Clocked full-scan circuit....
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This note was uploaded on 05/16/2011 for the course ENGINEERIN mp108 taught by Professor Elbarki during the Spring '08 term at Alexandria University.

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