94_pdfsam_VLSI TEST PRINCIPLES & ARCHITECTURES

94_pdfsam_VLSI TEST PRINCIPLES & ARCHITECTURES -...

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Design for Testability 63 X 2 Combinational logic 1 Combinational logic 2 X 1 Y 2 SO D + L 2 SRL 1 SRL 2 SRL 3 I C A B D I C A B D I C A B SI C 1 A B C 2 X 3 Y 1 (a) Combinational logic X 1 X 2 X 3 Y 2 Y 1 SO D + L 2 + L 1 SRL 1 SRL 2 SRL 3 I C A B D + L 2 I C + L 1 A B D + L 2 I C +L 1 A B SI C 1 A C 2 or B •• (b) + L 1 + L 2 + L 1 + L 2 + L 1 ± FIGURE 2.16 LSSD designs: (a) LSSD single-latch design, and (b) LSSD double-latch design. circuit is conducted using shift and capture operations, similar to a muxed-D full-scan circuit. The main difference is how these two operations are distin- guished. In a muxed-D full-scan circuit, a scan enable signal SE is used, as shown in Figure 2.14a. In an LSSD full-scan circuit, these two operations are distin-
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