Design for Testability63X2Combinational logic 1Combinational logic 2X1Y2SOD+L2SRL1SRL2SRL3ICABDICABDICABSIC1ABC2X3Y1(a)Combinational logicX1X2X3Y2Y1SOD+L2+L1SRL1SRL2SRL3ICABD+L2IC+L1ABD+L2IC+L1ABSIC1AC2or B•••••••••(b)+L1+L2+L1+L2+L1±FIGURE 2.16LSSD designs: (a) LSSD single-latch design, and (b) LSSD double-latch design.circuit is conducted using shift and capture operations, similar to a muxed-Dfull-scan circuit. The main difference is how these two operations are distin-guished. In a muxed-D full-scan circuit, a scan enable signalSEis used, as shownin Figure 2.14a. In an LSSD full-scan circuit, these two operations are distin-
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