95_pdfsam_VLSI TEST PRINCIPLES & ARCHITECTURES

95_pdfsam_VLSI TEST PRINCIPLES & ARCHITECTURES - 64...

Info iconThis preview shows page 1. Sign up to view the full content.

View Full Document Right Arrow Icon
64 VLSI Test Principles and Architectures As mentioned in Section 2.4.3, the operation of a polarity-hold SRL is race-free if clocks C and B as well as A and B are nonoverlapping. This characteristic is used to implement LSSD circuits that are guaranteed to have race-free operation in normal mode as well as in test mode. The required design rules [Eichelberger 1977] [Eichelberger 1978] are briefly summarized below: ± All storage elements must be polarity-hold latches. ± The latches are controlled by two or more nonoverlapping clocks such that any two latches where one feeds the other cannot have the same clock. ± A set of clock primary inputs must exist from which the clock ports of all SRLs are controlled either through a single clock tree or through logic that is gated by SRLs and/or non-clock primary inputs. In addition, the following three conditions should be satisfied: (1) all clock inputs to SRLs must be inactive when clock PIs are inactive, (2) the clock input to any SRL must be controlled
Background image of page 1
This is the end of the preview. Sign up to access the rest of the document.
Ask a homework question - tutors are online