Design for Testability65X2Combinational logicX3X1Y2Y1PIPPIPOPPODIQSFF1SISEDIQFF2SEDIQSFF3SISECKSISOFIGURE 2.17Partial-scan design.however, this may result in the additional complexity of routing two separate clocktrees during physical implementation.In order to reduce the test generation complexity, many approaches have beenproposed for determining the subset of storage elements for scan cell replacement.Scan cell selection can be conducted by using a functional partitioning approach, apipelined or feed-forward partial-scan design approach, or a balanced partial-scandesign approach.In thefunctional partitioningapproach, a circuit is viewed as being composedof a data path portion and a control portion. Typically, because storage elementson the data path portion cannot afford too much delay increase, especially whenreplaced with muxed-D scan cells, they are left out of the scan cell replacementprocess. On the other hand, storage elements in the control portion can be replaced
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Automatic test pattern generation, Directed acyclic graph, storage elements