96_pdfsam_VLSI TEST PRINCIPLES & ARCHITECTURES

96_pdfsam_VLSI TEST PRINCIPLES & ARCHITECTURES -...

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Design for Testability 65 X 2 Combinational logic X 3 X 1 Y 2 Y 1 PI PPI PO PPO DI Q SFF 1 SI SE DI Q FF 2 SE DI Q SFF 3 SI SE CK SI SO ± FIGURE 2.17 Partial-scan design. however, this may result in the additional complexity of routing two separate clock trees during physical implementation. In order to reduce the test generation complexity, many approaches have been proposed for determining the subset of storage elements for scan cell replacement. Scan cell selection can be conducted by using a functional partitioning approach, a pipelined or feed-forward partial-scan design approach, or a balanced partial-scan design approach. In the functional partitioning approach, a circuit is viewed as being composed of a data path portion and a control portion. Typically, because storage elements on the data path portion cannot afford too much delay increase, especially when replaced with muxed-D scan cells, they are left out of the scan cell replacement process. On the other hand, storage elements in the control portion can be replaced
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This note was uploaded on 05/16/2011 for the course ENGINEERIN mp108 taught by Professor Elbarki during the Spring '08 term at Alexandria University.

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