97_pdfsam_VLSI TEST PRINCIPLES & ARCHITECTURES

97_pdfsam_VLSI TEST PRINCIPLES & ARCHITECTURES - 66...

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66 VLSI Test Principles and Architectures FF 1 FF 2 C 1 C 2 FF 4 C 3 FF 5 FF 3 1 2 3 4 5 (a) (b) ± FIGURE 2.18 Sequential circuit and its structure graph: (a) sequential circuit, and (b) structure graph. The sequential depth of a circuit is equal to the maximum number of clock cycles that must be applied in order to control and observe values to and from all non- scan storage elements. In a full-scan design, because all scan cells can be controlled and observed directly in shift mode, the sequential depth of a full-scan circuit is 0. Similarly, the sequential depth of a combinational logic block is also 0. In a partial-scan design, replacing a storage element with a scan cell is equivalent to removing its corresponding vertex from the structure graph. In general, the difficulty of sequential ATPG is largely due to the existence of sequential feedback loops. By breaking all feedback loops, test generation for feedback-free sequential circuits becomes computationally efficient; hence, the scan
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