68VLSI Test Principles and Architecturesthere is no guarantee that the test application time can be reduced if a large numberof scan cells have to be updated for each test vector or the addresses of scan cellsto be consecutively accessed have little overlap.Recently, theprogressive random-access scan(PRAS) design [Baik 2005] wasproposed in an attempt to alleviate the problems associated with the traditionalRAS design. The PRAS scan cell, as shown in Figure 2.20a, has a structure similarto that of astatic random access memory(SRAM) cell or a grid-addressable latch[Susheel 2002], which has significantly smaller area and routing overhead than thetraditional scan cell design [Ando 1980]. In normal mode, all horizontal row enableREsignals are set to 0, forcing each scan cell to act as a normal D flip-flop. In testmode, to capture the test response from D, theREsignal is set to 0 and a pulse isapplied on clock, which causes the value on D to be loaded into the scan cell. To
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