99_pdfsam_VLSI TEST PRINCIPLES & ARCHITECTURES

99_pdfsam_VLSI TEST PRINCIPLES & ARCHITECTURES - 68...

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68 VLSI Test Principles and Architectures there is no guarantee that the test application time can be reduced if a large number of scan cells have to be updated for each test vector or the addresses of scan cells to be consecutively accessed have little overlap. Recently, the progressive random-access scan (PRAS) design [Baik 2005] was proposed in an attempt to alleviate the problems associated with the traditional RAS design. The PRAS scan cell, as shown in Figure 2.20a, has a structure similar to that of a static random access memory (SRAM) cell or a grid-addressable latch [Susheel 2002], which has significantly smaller area and routing overhead than the traditional scan cell design [Ando 1980]. In normal mode, all horizontal row enable RE signals are set to 0, forcing each scan cell to act as a normal D flip-flop. In test mode, to capture the test response from D, the RE signal is set to 0 and a pulse is applied on clock ± , which causes the value on D to be loaded into the scan cell. To
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This note was uploaded on 05/16/2011 for the course ENGINEERIN mp108 taught by Professor Elbarki during the Spring '08 term at Alexandria University.

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