104_pdfsam_VLSI TEST PRINCIPLES & ARCHITECTURES

104_pdfsam_VLSI TEST PRINCIPLES & ARCHITECTURES -...

Info iconThis preview shows page 1. Sign up to view the full content.

View Full Document Right Arrow Icon
Design for Testability 73 I/O CK BO BI DI Q SI SE I/O BO BI SE CK DI Q SI SE (a) (b) ± FIGURE 2.22 Fixing bidirectional I/O ports: (a) original circuit, and (b) modifed circuit. (a) (b) D CK CEN D D G EN GCK DFF LAT TM or SE B D Clock gating logic Q Q Q Q A D CK CEN D D D G EN GCK DFF LAT Clock gating logic Q Q Q Q ± FIGURE 2.23 Fixing gated clocks: (a) original circuit, and (b) modifed circuit. The clock gating function should be disabled at least during the shift operation.
Background image of page 1
This is the end of the preview. Sign up to access the rest of the document.

Unformatted text preview: Figure 2.23b shows how the clock gating can be disabled. In this example, an OR gate is used to force CEN to 1 using either the test mode signal TM or the scan enable signal SE . If TM is used, CEN will be held at 1 during the entire scan test operation (including the capture operation). This will make it impossible to detect...
View Full Document

This note was uploaded on 05/16/2011 for the course ENGINEERIN mp108 taught by Professor Elbarki during the Spring '08 term at Alexandria University.

Ask a homework question - tutors are online