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Unformatted text preview: Figure 2.23b shows how the clock gating can be disabled. In this example, an OR gate is used to force CEN to 1 using either the test mode signal TM or the scan enable signal SE . If TM is used, CEN will be held at 1 during the entire scan test operation (including the capture operation). This will make it impossible to detect...
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This note was uploaded on 05/16/2011 for the course ENGINEERIN mp108 taught by Professor Elbarki during the Spring '08 term at Alexandria University.
- Spring '08