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105_pdfsam_VLSI TEST PRINCIPLES & ARCHITECTURES

105_pdfsam_VLSI TEST PRINCIPLES & ARCHITECTURES -...

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74 VLSI Test Principles and Architectures faults in the clock gating logic, causing fault coverage loss. If SE is used, CEN will be held at 1 only during the shift operation but will be released during the capture operation; hence, higher fault coverage can be achieved but at the expense of increased test generation complexity. 2.6.4 Derived Clocks A derived clock is a clock signal generated internally from a storage element or a clock generator, such as phase-locked loop (PLL), frequency divider, or pulse generator. Because derived clocks are not directly controllable from primary inputs, in order to test the logic driven by these derived clocks, these clock signals must be bypassed during the entire test operation. An example is illustrated in Figure 2.24a, where the derived clock ICK drives the flip-flops DFF 1 and DFF 2 . In Figure 2.24b, a multiplexer selects CK , which is a clock directly controllable from a primary input, to drive DFF 1 and DFF 2 during the entire test operation when TM = 1. 2.6.5 Combinational Feedback Loops Depending on whether the number of inversions on a combinational feedback loop
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