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106_pdfsam_VLSI TEST PRINCIPLES & ARCHITECTURES

106_pdfsam_VLSI TEST PRINCIPLES & ARCHITECTURES -...

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Design for Testability 75 (a) D Combinational logic Combinational logic S (b) D S Combinational logic DI Q SI CK SI SE TM 0 1 Combinational logic DI Q SI 1 SE FIGURE 2.25 Fixing combinational feedback loops: (a) original circuit, and (b) modified circuit. 2.6.6 Asynchronous Set/Reset Signals Asynchronous set/reset signals of scan cells that are not directly controlled from primary inputs can prevent scan chains from shifting data properly. In order to avoid this problem, it is required that these asynchronous set/reset signals be forced to an inactive state during the shift operation. These asynchronous set/reset signals are typically referred to as being sequentially controlled. An example of a sequen- tially controlled reset signal RL is shown in Figure 2.26a. A method for fixing this asynchronous reset problem using an OR gate with an input tied to the test mode
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