106_pdfsam_VLSI TEST PRINCIPLES & ARCHITECTURES

106_pdfsam_VLSI TEST PRINCIPLES & ARCHITECTURES -...

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Unformatted text preview: Design for Testability 75 Co mbin ational logic Combinational l ogic D 0 1 D S Co mbin ational logic Combinational l ogic S Q DI DI SI SI SE SI SE CK TM (a) (b) FIGURE 2.25 Fixing combinational feedback loops: (a) original circuit, and (b) modified circuit. 2.6.6 Asynchronous Set/Reset Signals Asynchronous set/reset signals of scan cells that are not directly controlled from primary inputs can prevent scan chains from shifting data properly. In order to avoid this problem, it is required that these asynchronous set/reset signals be forced to an inactive state during the shift operation. These asynchronous set/reset signals are typically referred to as being sequentially controlled. An example of a sequentially controlled reset signal RL is shown in Figure 2.26a. A method for fixing this asynchronous reset problem using an OR gate with an input tied to the test mode signal TM is shown in Figure 2.26b. When TM = 1, the asynchronous reset signal RL of scan cell SFF2 is permanently disabled during the entire test operation. The disadvantage of using the test mode signal TM to disable asynchronous set/reset signals is that faults within the asynchronous set/reset logic cannot be tested. Using the scan enable signal SE instead of TM makes it possible to detect faults within the asynchronous set/reset logic, because during the capture operation TM SFF1 DI RL SI Q SE SFF2 R DI SI Q SE CK SFF1 DI SI Q SE RL SFF2 R DI SI Q SE CK (a) (b) FIGURE 2.26 Fixing asynchronous set/reset signals: (a) original circuit, and (b) modified circuit. ...
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This note was uploaded on 05/16/2011 for the course ENGINEERIN mp108 taught by Professor Elbarki during the Spring '08 term at Alexandria University.

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