107_pdfsam_VLSI TEST PRINCIPLES & ARCHITECTURES

107_pdfsam_VLSI TEST PRINCIPLES & ARCHITECTURES -...

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Unformatted text preview: 76 VLSI Test Principles and Architectures SE = these asynchronous set/reset signals are not forced to the inactive state. However, this might result in mismatches due to race conditions between the clock and asynchronous set/reset ports of the scan cells. A better solution is to use an independent reset enable signal RE to replace TM and to conduct test generation in two phases. In the first phase, RE is set to 1 during both shift and capture operations to test data faults through the DI port of the scan cells while all asynchronous set/reset signals are held inactive. In the second phase, RE is set to 1 during the shift operation and 0 during the capture operation without applying any clocks to test faults within the asynchronous set/reset logic. 2.7 SCAN DESIGN FLOW Although conceptually scan design is not difficult to understand, the practice of inserting scan into a design in order to turn it into a scan design requires careful planning. This often requires many circuit modifications where care must be takenplanning....
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