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108_pdfsam_VLSI TEST PRINCIPLES & ARCHITECTURES

108_pdfsam_VLSI TEST PRINCIPLES & ARCHITECTURES -...

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Design for Testability 77 Layout information Scan design Constraint & control information Original design Scan replacement Scan configuration Scan stitching Scan reordering Testable design Scan design rule checking and repair Test generation Scan extraction Scan verification Scan synthesis FIGURE 2.27 Typical scan design flow. under test. The steps shown in the scan design flow are described in the following subsections in more detail. 2.7.1 Scan Design Rule Checking and Repair The first step in implementing a scan design is to identify and repair all scan design rule violations in order to convert the original design into a testable design. Repairing these violations allows the testable design to meet target fault coverage requirements and guarantees that the scan design will operate correctly. These
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Unformatted text preview: scan design rules were described in the previous section. In addition to these scan design rules, certain clock control structures may have to be added for at-speed delay testing. Typically, scan design rule checking is also performed on the scan design after scan synthesis to confirm that no new violations exist. Upon successful completion of this step, the testable design must guarantee the correct shift and capture operations. During the shift operation, all clocks control-ling scan cells of the design are directly controllable from external pins. The clock skew between adjacent scan cells must be properly managed in order not to cause any shift failure. During the capture operation, fixing all scan design rule violations...
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