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Unformatted text preview: scan design rules were described in the previous section. In addition to these scan design rules, certain clock control structures may have to be added for at-speed delay testing. Typically, scan design rule checking is also performed on the scan design after scan synthesis to confirm that no new violations exist. Upon successful completion of this step, the testable design must guarantee the correct shift and capture operations. During the shift operation, all clocks control-ling scan cells of the design are directly controllable from external pins. The clock skew between adjacent scan cells must be properly managed in order not to cause any shift failure. During the capture operation, fixing all scan design rule violations...
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- Spring '08