109_pdfsam_VLSI TEST PRINCIPLES & ARCHITECTURES

109_pdfsam_VLSI TEST PRINCIPLES & ARCHITECTURES - 78...

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78 VLSI Test Principles and Architectures should guarantee correctness for data paths that originate and terminate within the same clock domain. For data paths that originate and terminate in different clock domains, additional care must be taken in terms of the way the clocks are applied in order to guarantee the success of the capture operation. This is mainly due to the fact that the clock skew between different clock domains is typically large. A data path originating in one clock domain and terminating in another might result in a mismatch when both clocks are applied simultaneously, and the clock skew between the two clocks is larger than the data path delay from the originating clock domain to the terminating clock domain. In order to avoid the mismatch, the timing governing the relationship of such a data path shown in the following equation must be observed: clock skew < data path delay + clock - to - Q delay ± originating clock ² If this is not the case, a mismatch may occur during the capture operation. In
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This note was uploaded on 05/16/2011 for the course ENGINEERIN mp108 taught by Professor Elbarki during the Spring '08 term at Alexandria University.

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