110_pdfsam_VLSI TEST PRINCIPLES & ARCHITECTURES

110_pdfsam_VLSI TEST PRINCIPLES & ARCHITECTURES -...

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Unformatted text preview: Design for Testability 79 CD 1 CCD 2 CCD 1 CD 3 CD 4 CD 5 CD 6 CD 7 CCD 3 CCD 4 CCD 5 CK 1 CK 2 CK 3 CD 1 CD 2 FIGURE 2.28 Clock grouping example. During the 1990s, this scan synthesis operation was typically performed using a separate set of scan synthesis tools, which were applied after the logic synthesis tool had synthesized a gate-level netlist out of an RTL description of the design. More recently, these scan synthesis features are being integrated into the logic synthesis tools, and scan designs are synthesized automatically from the RTL. The process of performing scan synthesis during logic synthesis is often referred to as one-pass synthesis or single-pass synthesis . The scan synthesis flow shown in Figure 2.27 includes four separate steps: (1) scan configuration, (2) scan replacement, (3) scan reordering, and (4) scan stitching. Each of these steps is described below in more detail....
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This note was uploaded on 05/16/2011 for the course ENGINEERIN mp108 taught by Professor Elbarki during the Spring '08 term at Alexandria University.

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