111_pdfsam_VLSI TEST PRINCIPLES & ARCHITECTURES

111_pdfsam_VLSI TEST PRINCIPLES & ARCHITECTURES -...

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80 VLSI Test Principles and Architectures wire load to the high-speed I/O pad may adversely affect the timing of the design. An additional limitation is the number of tester channels available for scan testing. The second issue regarding the types of scan cells to use typically depends on the process library. In general, for each type of storage element used, most process libraries have a corresponding scan cell type that closely resembles the functionality and timing of the storage element during normal operation. The third issue relates to which storage elements to exclude from scan synthesis. This is typically determined by investigating parts of the design where replacing storage elements with functionally equivalent scan cells can adversely affect timing. Therefore, storage elements lying on the critical paths of a design where the timing margin is very tight are often excluded from the scan replacement step, in order to guarantee that the manufactured device will meet the restricted timing. In addition,
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This note was uploaded on 05/16/2011 for the course ENGINEERIN mp108 taught by Professor Elbarki during the Spring '08 term at Alexandria University.

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