112_pdfsam_VLSI TEST PRINCIPLES & ARCHITECTURES

112_pdfsam_VLSI TEST PRINCIPLES & ARCHITECTURES - X...

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Design for Testability 81 (a) CK D 2 D 2 X Y D 1 D 3 D 1 D 3 (b) CK SC 1 SC 2 DI SI SE Q DI SI SE Q X SI Y ± FIGURE 2.29 Mixing negative-edge and positive-edge scan cells in a scan chain: (a) circuit structure, and (b) timing diagram. (a) (b) D Clock domain 1 CK 1 Lock-up latch CK 2 SC p SC q DI SI SE Q DI SI SE Q Clock domain 2
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Unformatted text preview: X Z SI Y Q CK 1 CK 2 D 2 D 2 X Y Z D 1 D 2 D 3 D 1 D 3 D 1 D 3 ± FIGURE 2.30 Adding a lock-up latch between cross-clock-domain scan cells: (a) circuit structure, and (b) timing diagram....
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