113_pdfsam_VLSI TEST PRINCIPLES & ARCHITECTURES

113_pdfsam_VLSI TEST PRINCIPLES & ARCHITECTURES -...

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82 VLSI Test Principles and Architectures domain CK 2 through a lock-up latch. The associated timing diagram is shown in Figure 2.30b, where CK 2 arrives after CK 1 , to demonstrate the effect of clock skew on cross-clock-domain scan cells. During each shift clock cycle, X will first take on the SI value at the rising CK 1 edge, then Z will take on the Y value at the rising CK 2 edge. Finally, the new X value is transferred to Y at the falling CK 1 edge to store the SCp contents. If CK 2 arrives earlier than CK 1 , Z will first take on the Y value at the rising CK 2 edge. Then, X will take on the SI value at the rising CK 1 edge. Finally, the new X value is transferred to Y at the falling CK 1 edge to store the SCp contents. In both cases, the lock-up latch design in Figure 2.30a allows correct shift operation regardless of whether CK 2 arrives earlier or later than CK 1 . It is important to note that this scheme works only when the clock skew between CK 1 and CK 2 is less than the width (duty cycle) of the clock pulse. If this is not the
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This note was uploaded on 05/16/2011 for the course ENGINEERIN mp108 taught by Professor Elbarki during the Spring '08 term at Alexandria University.

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