115_pdfsam_VLSI TEST PRINCIPLES & ARCHITECTURES

115_pdfsam_VLSI TEST PRINCIPLES & ARCHITECTURES -...

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84 VLSI Test Principles and Architectures step is often performed to verify the integrity of the scan chains, especially if any design changes are made to the scan design. Scan extraction is the process used for extracting all scan cell instances from all scan chains specified in the scan design. This procedure is performed by tracing the design for each scan chain to verify that all the connections are intact when the design is placed in shift mode. Scan extraction can also be used to prepare for the test generation process to identify the scan architecture of the design in cases where this information is not otherwise available. 2.7.4 Scan Verifcation When the physical implementation of the scan design is completed, including place- ment and routing of all the cells of the design, a timing file in standard delay format (SDF) is generated. This timing file resembles the timing behavior of the manufactured device. This is then used to verify that scan testing can be successfully performed on the manufactured scan design. Other than the trivial problems of scan chains being incorrectly stitched, veri-
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