86 VLSI Test Principles and Architectures 220.127.116.11 Verifying the Scan Capture Operation Verifying the scan capture operation involves simulating the scan design using a full-timing logic simulator during the capture operation. This is used to identify the location of any failing scan cells where the captured response does not match the expected response predicted by the zero-delay logic simulator used in test gener-ation or fault simulation. To reduce simulation time, a broadside-load testbench is often used, where a test pattern is loaded directly into all scan cells in the scan chains and only the capture cycle is simulated. Because the broadside-load test does not involve any shift cycle in the test pattern, broadside-load testbenches often include at least one shift cycle in the capture verification testbench to ensure that each test pattern can at least shift once. This requires loading the test pattern into the outputs of the previous scan cells, rather than directly into the outputs of the
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Automatic test pattern generation, Scan chain, Static timing analysis, 18.104.22.168