118_pdfsam_VLSI TEST PRINCIPLES & ARCHITECTURES

118_pdfsam_VLSI TEST PRINCIPLES & ARCHITECTURES -...

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Design for Testability 87 ± I/O pin cost —Scan design typically requires a dedicated test mode pin to indicate when scan testing is performed. Some designers have been able to get around this need by developing an initialization sequence that is capable of putting the design into test mode. Additional I/O cost is due to the possible performance degradation of pins where scan inputs and scan outputs are shared. ± Performance degradation cost —The additional scan input of a scan cell may require placing an additional delay on the functional path. The effects of this delay can be alleviated by embedding the scan replacement step in logic/scan synthesis such that the logic optimization process can be aggressively per- formed to reduce the effect of the added delay. ± Design effort cost —Implementing scan requires additional steps to be added to the typical design flow to perform scan design rule checking and repair, scan synthesis, scan extraction, and scan verification. Additional effort may
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This note was uploaded on 05/16/2011 for the course ENGINEERIN mp108 taught by Professor Elbarki during the Spring '08 term at Alexandria University.

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