Info iconThis preview shows page 1. Sign up to view the full content.

View Full Document Right Arrow Icon
88 VLSI Test Principles and Architectures LA 1 D C DI Q SDI CK SFF 1 SI SE SE Q UPDATE LA 2 D C DI Q SFF 2 SI SE Q X 2 Combinational logic X n X 1 Y 2 Y m Y 1 LA s D C DI Q SFF s SI SE Q ± FIGURE 2.31 Enhanced-scan architecture. by the scan cells. For a muxed-D scan cell or a clocked-scan cell, this is achieved through the addition of a D latch. Figure 2.31 shows a general enhanced-scan architecture using muxed-D scan cells. In this figure, in order to apply a pair of test vectors <V 1 , V 2 > to the design, the first test vector V 1 is first shifted into the scan cells ( SFF 1 SFF s ) and then stored into the additional latches ( LA 1 LA s ) when the UPDATE signal is set to 1. Next, the second test vector V 2 is shifted into the scan cells while the UPDATE signal is set to 0, in order to preserve the V 1 values in the latches ( LA 1 LA s ). Once the second vector V 2 is shifted in, the UPDATE signal is applied to change V 1 to V 2 while capturing the output response at-speed into the scan cells by applying
Background image of page 1
This is the end of the preview. Sign up to access the rest of the document.

This note was uploaded on 05/16/2011 for the course ENGINEERIN mp108 taught by Professor Elbarki during the Spring '08 term at Alexandria University.

Ask a homework question - tutors are online