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Design for Testability 89 CK 1D C1 C2 2D Q 1D C1 C2 2D Q 1D C1 C2 2D Q 1D 2D C1 C2 Q 1D 2D 1D 2D Q Q UCK SDI C1 C2 C1 C2 DCK TCK SDO L 1 L 2 L s SFF 1 SFF 2 SFF s Combinational logic X n X 1 Y 2 Y m Y 1 X 2 ± FIGURE 2.32 Scan-set architecture. of the circuit. This is done by adding a scan cell to each storage element of interest in the circuit. These scan cells are connected as one or more scan chains that can be used to shift in and shift out any required test data or internal state snapshot of the design. A snapshot scan design technique, called scan set , was proposed in [Stewart 1978]. An example of scan-set architecture implemented by adding clocked-scan cells to the system latches (two-port D latches) for snapshot scan is shown in Figure 2.32. In this figure, four different operations are possible: (1) Test data can be shifted into and out of the scan cells ( SFF 1 SFF s ) from the SDI and SDO pins, respectively, using TCK . (2) The test data can be transferred to the system latches (
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