122_pdfsam_VLSI TEST PRINCIPLES & ARCHITECTURES

122_pdfsam_VLSI TEST PRINCIPLES & ARCHITECTURES -...

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Design for Testability 91 LA 1D C1 2D C2 Q C1 1D Q LB 1D C1 2D C2 Q O 2 Scan portion System flip-flop O 1 C1 1D Q CLK D UPDATE CAPTURE SCA SI SCB C-element Keeper TEST Q SO PH 2 PH 1 ± FIGURE 2.33 Error-resilient scan cell. TABLE 2.8 ± C-Element Truth Table O 1 O 2 Q 0 0 1 1 1 0 0 1 Previous value retained 1 0 Previous value retained and O 2 are unequal, the output of the C-element keeps its previous value. During this mode ,a0is applied to the SCA , SCB , and UPDATE signals, anda1is applied to the CAPTURE signal. This converts the scan portion into a master-slave flip-flop that operates as a shadow of the system flip-flop. That is, whenever the functional clock CLK is applied, the same logic value is captured into both the system flip-flop and the scan portion. When CLK is 0, the outputs of latches PH 1 and LB hold their previous logic values. If a soft error occurs either at PH 1 or at LB , O 1 and O 2 will
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Unformatted text preview: CLK is 1, the outputs of latches PH 2 and LA hold their previous logic values, and the logic values drive O 1 and O 2 , respectively. If a soft error occurs either at PH 2 or at LA , O 1 and O 2 will have different logic values. In both cases, unless such a soft error occurs after the correct logic value passes through the C-element and reaches the keeper, the soft error will not propagate to the output Q and the keeper will retain the correct logic value at Q . Error-resilient scan is one of the first online test techniques developed for soft error protection. While the error-resilient scan cell requires more test signals, clocks, and area overhead than conventional scan cells, the technique paves the way...
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This note was uploaded on 05/16/2011 for the course ENGINEERIN mp108 taught by Professor Elbarki during the Spring '08 term at Alexandria University.

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