92VLSI Test Principles and Architecturesto develop more advanced error-resilient and error-tolerant scan and logic BISTarchitectures to cope with the physical failures of the nanometer age.2.9RTL DESIGN FOR TESTABILITYDuring the 1990s, the testability of a circuit was primarily assessed and improvedat the gate level. The reason was because the circuits were not too large that thelogic/scan synthesis process took an unreasonable amount of time. As device sizegrows toward tens to hundreds of millions of transistors, tight timing, potentialyield loss, and low power issues begin to pose serious challenges. When combinedwith increased core reusability and time-to-market pressure, it is becoming imper-ative that most, if not all, testability issues be fixed at the RTL. This allows thelogic/scan synthesis tool and the physical synthesis tool, which takes physical lay-out information into consideration, to optimize area, power, and timing after DFTrepairs are made. Fixing DFT problems at the RTL also allows designers to create
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