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124_pdfsam_VLSI TEST PRINCIPLES & ARCHITECTURES

124_pdfsam_VLSI TEST PRINCIPLES & ARCHITECTURES -...

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Design for Testability 93 Testable RTL design RTL design Testability repair Scan design Logic/scan synthesis FIGURE 2.35 RTL testability repair design flow. advanced DFT features at the RTL, and later integrating them with scan at the gate level. In the following, we describe the RTL DFT problems by focusing mainly on scan design. Some modern synthesis tools now incorporate testability repair and scan synthe- sis as part of the logic synthesis process, such that a testable design free of scan rule violations is generated automatically. In this case, if the DFT fixes made are acceptable and do not have to be incorporated into the RTL, the flow can proceed directly to test generation and scan verification. 2.9.1 RTL Scan Design Rule Checking and Repair In order to perform scan design rule checking and repair at the RTL, a fast syn- thesis step of the RTL is usually performed first. In fast synthesis, combinational RTL code is mapped onto combinational primitives and high-level models, such as adders and multipliers. This allows us to identify all possible scan design rule
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