94VLSI Test Principles and Architecturesalways @(posedge clk)if (q ==4'b1111)clk_15 <= 1;elsebeginclk_15 <= 0;q<= q + 1;endalways @(posedge clk_15)d < = start; clkQQstartdDclk_15(a)[email protected](posedge clk)if(q == 4'b1111)clk_15 <= 1;elsebeginclk_15 <= 0;q <= q + 1; endassign clk_test = (TM)? clk : clk_15;always @(posedge clk_test)d <= start;(c)(b)(d)clkQQstartd Dclk_1501TMclk_testFIGURE 2.36Automatic repair of a generated clock violation at the RTL: (a) generated clock (RTL code), (b) generatedclock (schematic), (c) generated clock repair (RTL code), and (d) generated clock repair (schematic).shows a schematic of the flip-flop generating theclk_15 signal, as well as the flip-flop driven by the generated clock, which is likely to be the structure synthesizedout of the RTL using a logic synthesis tool. This scan design rule violation canbe fixed using the test mode signalTMby modifying the RTL code as shown inFigure 2.36c. The schematic for the modified RTL code is shown in Figure 2.36d.2.9.2RTL Scan SynthesisWhen storage elements have been identified during RTL scan design rule check-
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