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94 VLSI Test Principles and Architectures always @(posedge clk) if (q ==4'b1111) clk_15 <= 1; else begin clk_15 <= 0; q < = q + 1; end always @(posedge clk_15) d < = start; clk Q Q start d D clk_ 15 (a) [email protected](posedge clk) if(q == 4'b1111) clk_15 <= 1; else begin clk_15 <= 0; q <= q + 1; end assign clk_test = (TM)? clk : clk_15; always @(posedge clk_test) d <= start; (c) (b) (d) clk Q Q start d D clk_ 15 0 1 TM clk_test FIGURE 2.36 Automatic repair of a generated clock violation at the RTL: (a) generated clock (RTL code), (b) generated clock (schematic), (c) generated clock repair (RTL code), and (d) generated clock repair (schematic). shows a schematic of the flip-flop generating the clk _15 signal, as well as the flip- flop driven by the generated clock, which is likely to be the structure synthesized out of the RTL using a logic synthesis tool. This scan design rule violation can be fixed using the test mode signal TM by modifying the RTL code as shown in Figure 2.36c. The schematic for the modified RTL code is shown in Figure 2.36d. 2.9.2 RTL Scan Synthesis When storage elements have been identified during RTL scan design rule check-
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