126_pdfsam_VLSI TEST PRINCIPLES & ARCHITECTURES

126_pdfsam_VLSI TEST PRINCIPLES & ARCHITECTURES -...

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Design for Testability 95 or single-pass synthesis step is performed using the RTL design flow, as shown in Figure 2.35. Several additional steps are actually performed in order to identify the storage elements in the RTL design. First, all clocks are identified, either explicitly by tracing from specified clock signal names, or implicitly by analyzing the sensitivity list of all “always” blocks. When the clocks have been identified, all registers, each consisting of one or more storage elements in the RTL design, are inferred by analyzing all “assign” statements to determine which assignments can be mapped onto a register while keeping track of the clock domain to which each register belongs. In addition, the clock polarity of each register is determined. When all registers have been identified and each converted into its scan equiva- lent at the RTL, the next step is to stitch these individual scan cells into one or more scan chains. One approach is to allocate scan cells to different scan chains based
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This note was uploaded on 05/16/2011 for the course ENGINEERIN mp108 taught by Professor Elbarki during the Spring '08 term at Alexandria University.

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