96 VLSI Test Principles and Architectures was to quantify testability. This led to the development of testability analysis, used to identify design areas of poor controllability and observability. These techniques have since proven effective in test generation, logic built-in self-test (BIST), and fault coverage estimation. When it was recognized that generating test patterns for a sequential circuit was a much more difficult problem than generating test patterns for a combinational cir-cuit, ad hoc DFT techniques were proposed but were met with limited success. Scan design, which has proven to be the most powerful DFT technique ever invented, allowed the transformation of sequential circuit testing into combinational circuit testing and has since become an industry standard. In this chapter, we have presented a comprehensive discussion of scan design. This included scan cell designs, scan architectures, scan design rules, and a typical scan design flow. The RTL DFT techniques that include RTL testability analysis
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