Design for Testability 97 2.6 (Test Point Insertion) Show an implementation where a single observation point is used to observe the three low-observability nodes A , B , and C in Figure 2.5 using XOR gates. 2.7 (Clocked-Scan Cell) Show a possible gate-level implementation of the clocked-scan cell shown in Figure 2.11a. 2.8 (LSSD Scan Cell) Show a possible CMOS implementation of the LSSD scan cell shown in Figure 2.12a. 2.9 (Full-Scan Design) Calculate the number of clock cycles required for testing a full-scan design with n test vectors. Assume that the full-scan design has m scan chains, each having the same length L , and that scan testing is conducted in the way shown in Figure 2.14b. 2.10 (Full-Scan Design) Explain the main differences between an LSSD single-latch design and an LSSD double-latch design. 2.11 (Random-Access Scan) Assume that a sequential circuit with n storage ele-ments has been reconfigured as a full-scan design as shown in Figure 2.14a and a random-access scan design as shown in Figure 2.19. In addition, assume
This is the end of the preview. Sign up
access the rest of the document.