129_pdfsam_VLSI TEST PRINCIPLES & ARCHITECTURES

129_pdfsam_VLSI TEST PRINCIPLES & ARCHITECTURES -...

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98 VLSI Test Principles and Architectures two cross-clock-domain scan cells into one single scan chain using a lock-up latch. If not, can it be done using a lock-up flip-flop instead? 2.16 (Scan Stitching) Use examples to show why a scan chain may not be able to perform the shift operation properly if two neighboring scan cells in the scan chain are too close to or too far from each other. Also describe how to solve these problems. 2.17 (Test Signal) Describe the difference between the test mode signal TM and the scan enable signal SE used in scan testing. 2.18 (Clock Grouping) Show an algorithm to find the smallest number of clock groups in clocking grouping. 2.19 (RTL Testability Enhancement) Read the following Verilog HDL code and draw its schematic. Then determine if there is any scan design rule violation. If there is any violation, modify the RTL code to fix the problem, then draw the schematic of the modified RTL code. reg [3:0] tri_en; always @(posedge clk) begin case (bus_sel) 0: tri_en[0] = 1’bl; 1: tri_en[1] = 1’bl;
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Unformatted text preview: 2: tri_en[2] = 1’bl; 3: tri_en[3] = 1’bl; endcase end assign dbus = (tri_en[0])? d1 : 8’bz; assign dbus = (tri_en[1])? d2 : 8’bz; assign dbus = (tri_en[2])? d3 : 8’bz; assign dbus = (tri_en[3])? d4 : 8’bz; 2.20 (A Design Practice) Use the scan design rule checking programs and user’s manuals contained on the companion Web site to show if you can detect any asynchronous set/reset signal violations and bus contention. Try to redesign a Verilog circuit to include such violations. Then, fix the violations by hand, and see whether the problems disappear. 2.21 (A Design Practice) Use the scan synthesis programs and user’s manuals contained on the companion Web site to convert the two ISCAS-1989 benchmark circuits s27 and s38417 [Brglez 1989] into scan designs. Perform scan extraction and then run Verilog flush tests and broadside-load tests on the scan designs to verify whether the generated testbenches pass Verilog simulation....
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