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Unformatted text preview: 2: tri_en = 1’bl; 3: tri_en = 1’bl; endcase end assign dbus = (tri_en)? d1 : 8’bz; assign dbus = (tri_en)? d2 : 8’bz; assign dbus = (tri_en)? d3 : 8’bz; assign dbus = (tri_en)? d4 : 8’bz; 2.20 (A Design Practice) Use the scan design rule checking programs and user’s manuals contained on the companion Web site to show if you can detect any asynchronous set/reset signal violations and bus contention. Try to redesign a Verilog circuit to include such violations. Then, fix the violations by hand, and see whether the problems disappear. 2.21 (A Design Practice) Use the scan synthesis programs and user’s manuals contained on the companion Web site to convert the two ISCAS-1989 benchmark circuits s27 and s38417 [Brglez 1989] into scan designs. Perform scan extraction and then run Verilog flush tests and broadside-load tests on the scan designs to verify whether the generated testbenches pass Verilog simulation....
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- Spring '08