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130_pdfsam_VLSI TEST PRINCIPLES & ARCHITECTURES

130_pdfsam_VLSI TEST PRINCIPLES & ARCHITECTURES -...

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Design for Testability 99 Acknowledgments The authors wish to thank Prof. Xinghao Chen of The City College and Graduate Center of The City University of New York for contributing the Testability Analysis section, and Shianling Wu of SynTest Technologies for contributing a portion of the RTL Design for Testability section, as well as Dwayne Burek of Magma Design Automation, Dr. Augusli Kifli of Faraday Technology, Thomas Wilderotter of Synopsys, and Xiangfeng Li and Fangfang Li of SynTest Technologies for reviewing the text and providing valuable comments. References R2.0—Books [Abramovici 1994] M. Abramovici, M. A. Breuer, and A. D. Friedman, Digital Systems Testing and Testable Design , IEEE Press, Piscataway, NJ, 1994. [Bushnell 2000] M. L. Bushnell and V. D. Agrawal, Essentials of Electronic Testing for Digital, Memory and Mixed-Signal VLSI Circuits , Springer Science, New York, 2000. [Crouch 1999] A. Crouch, Design for Test for Digital IC’s and Embedded Core Systems , Prentice Hall, Upper Saddle River, NJ, 1999.
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  • Spring '08
  • elbarki
  • Electronic design automation, IEEE Trans, V. D. Agrawal, H. Fujiwara, Testability Analysis section, IEEE Standard Description

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