132_pdfsam_VLSI TEST PRINCIPLES & ARCHITECTURES

132_pdfsam_VLSI TEST PRINCIPLES & ARCHITECTURES -...

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Design for Testability 101 R2.4—Scan Cell Designs [DasGupta 1982] S. DasGupta, P. Goel, R. G. Walter, and T. W. Williams, A variation of LSSD and its implications on design and test pattern generation in VLSI, in Proc. Int. Test Conf. , November 1982, pp. 63–66. [Eichelberger 1977] E. B. Eichelberger and T. W. Williams, A logic design structure for LSI testability, in Proc. Des. Automat. Conf. , June 1977, pp. 462–468. [Eichelberger 1978] E. B. Eichelberger and T. W. Williams, A logic design structure for LSI testability, J. Des. Automat. Fault-Tolerant Comput. , 2(2), 165–178, 1978. R2.5—Scan Architectures [Abadir 1985] M. S. Abadir and M. A. Breuer, A knowledge-based system for designing testable VLSI chips, IEEE Design Test Comput. , 2(4), 56–68, 1985. [Agrawal 1987] V. D. Agrawal, K.-T. Cheng, D. D. Johnson, and T. Lin, A complete solution to the partial scan problem, in Proc. Int. Test Conf. , September 1987, pp. 44–51. [Agrawal 1995] V. D. Agrawal, Special issue on partial scan methods, Vol. 7, No. 1/2,
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