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133_pdfsam_VLSI TEST PRINCIPLES & ARCHITECTURES

133_pdfsam_VLSI TEST PRINCIPLES & ARCHITECTURES -...

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102 VLSI Test Principles and Architectures [Trischler 1980] E. Trischler, Incomplete scan path with an automatic test generation methodology, in Proc. Int. Test Conf. , November 1980, pp. 153–162. [Williams 1983] T. W. Williams and K. P. Parker, Design for testability: A survey, Proc. IEEE , 71(1), 98–112, 1983. R2.6—Scan Design Rules [Cheung 1996] B. Cheung and L.-T. Wang, The seven deadly sins of scan-based designs, Integrated Syst. Des. , August 1996 (www.eetimes.com/editorial/1997/test9708.html). R2.7—Scan Design Flow [Barbagallo 1996] S. Barbagallo, M. Bodoni, D. Medina, F. Corno, P. Prinetto, and M. Sonza Reorda, Scan insertion criteria for low design impact, in Proc. VLSI Test Symp. , April 1996, pp. 26–31. [Duggirala 2002] S. Duggirala, R. Kapur, and T. W. Williams, System and Method for High- Level Test Planning for Layout, U.S. Patent No. 6,434,733, August 13, 2002. [Duggirala 2004] S. Duggirala, R. Kapur, and T. W. Williams, System and Method for High- Level Test Planning for Layout, U.S. Patent No. 6,766,501, July 20, 2004. R2.8—Special-Purpose Scan Designs [Cheng 1991] K. Cheng, S. Devadas, and K. Keutzer, A partial enhanced-scan approach to
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